EPEPS 2022: San Jose CA
IEEE
Special Session - Co-Design for Chiplets
Monday, October 10, 1:30 pm - 3:20 pm

Talk 1:
Future of Simulation Driven Innovation in Nanotechnology

Prith Banerjee,
CTO
Ansys

Prith Banerjee is Chief Technology Officer at ANSYS, a leader in engineering simulation. Prior to that, he was CTO of Schneider Electric, CTO of ABB, Managing Director of R&D at Accenture, and Director of HP Labs. Previously he spent 20 years in academia as Professor, Chairman and Dean at the University of Illinois and Northwestern University. He has founded two companies, AccelChip and Binachip. Banerjee currently serves on the Board of Directors of Turntide Technologies. In the past, he has served on the Board of Cray, CUBIC. and Anita Borg Institute, and the Technical Advisory Boards of Ambit, Atrenta, Calypto, Cypress, Ingram Micro, and Virsec. He is a Fellow of the AAAS, ACM and IEEE. He is the author of more than 350 papers and a book entitled INNOVATION FACTORY. He received a B.Tech. in electronics engineering from the Indian Institute of Technology, Kharagpur, and an M.S. and Ph.D. in electrical engineering from the University of Illinois, Urbana.

Talk 2:
When Chips Become Systems; The Challenges of Designing Advanced 2.5D and 3D Packages

John Park,
Product Management Group Director
Cadence Design Systems

John Park brings over 40 years of design and EDA experience to his role as Product Management Group Director for Advanced Semiconductor Packaging at Cadence Design Systems. In this role, John leads a team responsible for defining cross-domain solutions and methodologies for IC, package & PCB co-design and analysis. Over the past several years, John has authored numerous publications on emerging trends in multi-chip(let) package design and analysis.

Talk 3:
Chiplet Based Designs: An SI/PI Perspective

Nithya Sankaran,
Principal Engineer
NVIDIA

Nithya Sankaran Nithya Sankaran is a principal engineer in the signal integrity team at NVIDIA. She received her MS and Ph.D. degrees from Georgia Tech, Atlanta. Her research interests include high speed interconnects and on-chip/system level power integrity

Talk 4:
The Open Domain-Specific Architecture: A D2D Interface Optimized for Die Disaggregation

Bapi Vinnakota,
Project Lead
ODSA

Bapi Vinnakota leads the Open Domain-Specific Architecture sub-project, in the Open Compute Project. The ODSA has active volunteers from over 50 companies and aims to define an open chiplet marketplace. The ODSA recently announced the Bunch of Wires interface being implemented by several companies and has several chiplet-related activities in flight.
After a Ph.D. at Princeton, he taught at the University of Minnesota for a decade. He has also worked at Intel, Broadcom and in algorithmic trading..

Panelist:
Co-Design for Chiplets

Ravi Agarwal,
Infrastructure Group
META

Ravi Agarwal received PhD dual major in Materials Science & Engineering and Polymer Science from North Carolina State University and MBA from University of California Berkeley. Ravi has 16+ years of High Tech industry experience in the areas of advanced packaging, supply chain strategy, product management, and business operations. He has co-authored more than 20 journal and conference publications, and holds 6 U.S. patents. Ravi is a technical sourcing manager at Meta Infrastructure group. In this role, he is responsible for driving AI/ML chip architecture using advanced packaging to meet Meta future workloads. He is driving Chiplet Business workstream in Open Domain-Specific Architecture (ODSA) Sub-Project within Open Compute Project (OCP) working with ecosystem partners to enable Chiplet marketplace.