EPEPS 2018: San Jose, California
IEEE
Keynote Presentation:
System design in a post-Moore’s world: looking for flexibility, performance, and efficiency in all the right places

Dr. Ron Ho, Senior Director of Programmable Hardware IO Systems
Intel

Abstract: As we pivot to the economic inevitability of a post-Moore’s world, we need innovative ways to continue running an ever-expanding set of user workloads. Customized silicon solutions offer tantalizingly good performance and energy efficiency but at a development cost incompatible with constantly changing markets. The reconfigurability of FPGAs makes them a compelling option, but at a high performance and efficiency cost. In this talk we will explore some of the design, packaging, and system implications of future highly integrated silicon solutions.

Ron Ho built CPUs at Intel from 1993-2003, from the 486 to Pentium/PentiumII to Itanium3 processors. From 2003-2014 he was at Sun/Oracle where he worked on capacitively and optically coupled IO, 3D-stacked memories, and big-data appliance accelerators. In late 2014 he joined Altera, now Intel’s Programmable Solutions Group, where he is currently Sr. Director of Programmable Hardware IO Systems, responsible for circuits that carry bits off the FPGA to the outside world. Ron received his Ph.D. in E.E. from Stanford University. He has 60 U.S. patents and has co-authored 100 publications.