Return2020 IEEE Electrical Performance of Electronic Packages and Systems (EPEPS), Virtual Event - October 5-7, 2020 - Final Program

Final Program - Return

Monday, October 5, 2020 Tuesday, October 6, 2020 Wednesday, October 7, 2020
7:50 - 8:00 am Pacific, Conference Kickoff
7:50 - 8:00 am Pacific, Welcome
7:50 - 8:00 am Pacific, Welcome
8:00 - 9:00 am Pacific
Keynote I - Meeting the Challenge of Building a Scalable Quantum Computer
(Live Q&A - 8:50 - 9:00 am Pacific)
Jim Held
Intel Corporation
9:00 - 10:20 am Pacific
Session M1A - High-Speed Links I
Session Chair:
Henning Braunisch, Intel

  • 9:00 - 9:15 am Pacific - M1A.1. PCIe Gen-5 Design Challenges of High-Speed Servers [115]
    Mallikarjun Vasa, Chen Ching-Huei, Kumar Sanjay, Ching-Huei Chen, Mutnury Bhyrav
    Dell
  • 9:15 - 9:30 am Pacific - M1A.2. Measurement Uncertainty Propagation in the Validation of High-Speed Interconnects [24]
    Cemil Geyik*, Michael Hill*, Zhichao Zhang*, Kemal Aygun*, Aberle James+
    *Intel,
    +ASU
  • 9:30 - 9:45 am Pacific - M1A.3. Rx Equalization for a High-Speed Channel Based on Bayesian Active Learning Using Dropout [128]
    Xianbo Yang**, Junyan Tang**, Hakki Torun*, Wiren Becker**, , Jose Hejase+, Madhavan Swaminathan*
    *Georgia Tech,
    +Nvidia,
    **IBM
  • 9:45 - 10:00 am Pacific - M1A.4. Post-Fec BER Performance Analysis for Multi-Stage PAM4 Systems [34]
    Xiaoqing Dong+, Chunxing Huang*,
    *Zhongzeling Electronics,
    +Xilinx
  • 10:00 - 10:20 am Pacific - Live Q&A1
    Panel of Presenters
9:00 - 10:20 am Pacific
Session M1B - Advanced CAD I
Session Chair:
Stefano Grivet-Talocia, Politecnico di Torino
  • 9:00 - 9:15 am Pacific - M1B.1. Hyperparameter determination in multivariate macromodeling based on radial basis functions [72] (Student competition)
    Alessandro Zanco, Stefano Grivet-Talocia
    Politecnico di Torino
  • 9:15 - 9:30 am Pacific - M1B.2. Augmented PEEC for direct time domain thermal and power estimation of Integrated Voltage Regulator Architectures arising in Heterogeneous Integration [2] (Student competition)
    Venkatesh Avula, Vanessa Smet, Yogendra Joshi, Madhavan Swaminathan
    * Georgia Tech
  • 9:30 - 9:45 am Pacific - M1B.3. Accelerated Boundary Element Modeling of Lossy Conductors in Layered Media with a Single-Source Surface Impedance Operator [80] (Student competition)
    Shashwat Sharma, Piero Triverio
    University of Toronto
  • 9:45 - 10:00 am Pacific - M1B.4. Predictor-Corrector Algorithm with Embedded Dimension Reduction for Uncertainty Quantification of MWCNT On-Chip Interconnect Networks [87] (Student competition)
    Surila Guglani, Sourajeet Roy
    IIT Roorkee
  • 10:00 - 10:20 am Pacific - Live Q&A2
    Panel of Presenters

10:20 - 10:30 am Pacific
Break

10:30 - 11:20 am Pacific
Tutorial I
Moderator:
Swagato Chakraborty, Mentor
How to Find and Validate Power Rail Resonances
Heidi Barnes**, Steve Sandler**, and Jack Carrel+
*Keysight
**Picotest
+Xilinx
11:20 - 11:30 am Pacific
Live Q&A1


11:30 am - 12:50 pm Pacific
Session M2A - Power Integrity
Session Chair:
Matt Doyle, IBM

  • 11:30 - 11:45 am Pacific - M2A.1. Extracting the Dynamic Current of a Power Delivery Network [65]
    Heidi Barnes*, Steve Sandler**, Jack Carrel*
    *Keysight Technologies,
    **Picotest
    +Xilinx
  • 11:45 am - 12:00 pm Pacific - M2A.2. A Novel Multipin Gauss-Newton Method for Performance Evaluation of Decoupling Capacitors [92]
    Ihsan Erdin*, Ram Achar**
    *Celestica,
    **Carleton University
  • 12:00 - 12:15 pm Pacific - M2A.3. A Non-Random Exploration based Method for the Optimization of Capacitors in Power Delivery Networks [41]
    Seunghyup Han, Madhavan Swaminathan
    Georgia Tech
  • 12:15 - 12:30 pm Pacific - M2A.4. A Parallel-in-Time Circuit Simulator for Power Delivery Networks with Nonlinear Load Models [47]
    Chung-Kuan Cheng*, Chia-Tung Ho*, Chao Jiao+, Xinyuan Wang*, Zhiyu Zeng+, Xin Zhan+,
    *UCSD,
    +Cadence
  • 12:30 - 12:50 pm Pacific - Live Q&A1
    Panel of Presenters
10:30 - 11:20 am Pacific
Tutorial II
Moderator:
Zhiguo Qian, Intel
Challenges and solutions for efficient 3D EM analysis of IC-Package-Board problems
Amir Ahmed Asif
Cadence
11:20 - 11:30 am Pacific
Live Q&A2


11:30 am - 12:50 pm Pacific
Session M2B - Applied Electromagnetics
Session Chair:
Ram Achar, Carleton University

  • 11:30 - 11:45 am Pacific - M2B.1. High-Dimensional Uncertainty Quantification via Active and Rank-Adaptive Tensor Regression [30] (Student competition)
    Zichang He, Zheng Zhang
    UCSB
  • 11:45 am - 12:00 pm Pacific - M2B.2. Analysis of the Influence of Roughness on the Propagation Constant of a Waveguide via Two Sparse Stochastic Methods [64] (Student competition)
    Ruben Waeytens, Dries Bosman, Martijn Huynen, Michiel Gossye, Hendrik Rogier, Dries Vande Ginste+
    Ghent University/Imec,
  • 12:00 - 12:15 pm Pacific - M2B.3. On the Accuracy of Cross-Talk Modeling in High-Speed Digital Circuits Using the Accelerated Boundary Element Method [108]
    Dongwei Li, Giacomo Bianconi , Swagato Chakraborty
    Mentor
  • 12:15 - 12:30 pm Pacific - M2B.4. A Comparison of Finite vs. Infinite Plane Models of Reference Conductors in Electronic Packages [105]
    Yiru Jeong, Ali Yilmaz
    UT Austin
  • 12:30 - 12:50 am Pacific - Live Q&A2
    Panel of Presenters

12:50 - 1:00 pm Pacific
Day 1 Wrap Up
8:00 - 9:00 am Pacific
Keynote II - High Speed and Large Bandwidth Server Computer Bus Links: Past Milestones, Current State of The Art and Future Directions
(Live Q&A - 8:50 - 9:00 am Pacific)
Daniel Dreps
IBM
9:00 - 10:20 am Pacific
Session T1A - High-Speed Links II
Session Chair:
Kevin Gu, IBM

  • 9:00 - 9:15 am Pacific - T1A.1. Via Design Optimization for High Speed Differential Interconnects on Circuit Boards [46]
    Armen Vardapetyan, Ong Chong-Jin
    Intel Corporation
  • 9:15 - 9:30 am Pacific - T1A.2. Signal Integrity Characterization of Channels With Asymmetric Via Stubs [44]
    Yanyan Zhang, Mahesh Bohra, Nam Pham , Pavel Paladhi, Dale Becker, Daniel Dreps
    IBM
  • 9:30 - 9:45 am Pacific - T1A.3. High-Speed Link Design Optimization Using Machine Learning SVR-AS Method [93] (Student competition)
    Hanzhi Ma+, Andreas C. Cangellaris*, Er-Ping Li+, Xu Chen*
    *UIUC,
    +Zhejiang University
  • 9:45 - 10:00 am Pacific - T1A.4. ANN Performance for the Prediction of High-Speed Digital Interconnects over Multiple PCBs [38] (Student competition)
    Katharina Scharff, Christian Morten Schierholz, Cheng Yang, Christian Schuster
    Hamburg University of Technology
  • 10:00 - 10:20 am Pacific - Live Q&A1
    Panel of Presenters
9:00 - 10:20 am Pacific
Session T1B - Advanced CAD II
Session Chair:
Xu Chen, UIUC

  • 9:00 - 9:15 am Pacific - T1B.1. A Shielded-Block Preconditioner for Reduced-Domain Layered-Medium Integral-Equation Methods [131]
    Chang Liu*, Ali Yilmaz+
    *Cadence
    +UT Austin
  • 9:15 -9:30 am Pacific - T1B.2. An Efficient and Parallel Electromagnetic Solver for Complex Interconnects in Layered Media [84] (Student competition)
    Damian Marek, Shashwat Sharma, Piero Triverio
    University of Toronto
  • 9:30 - 9:45 am Pacific - T1B.3. On Dissipativity Conditions for Linearized Models of Locally Active Circuit Blocks [35] (Student competition)
    Tommaso Bradde*, Stefano Grivet-Talocia*, Giuseppe Carlo Calafiore*, Anton Proskurnikov*, Zohaib Mahmood+, Luca Daniel**
    *Politecnico di Torino,
    +NanoSemi, Inc.,
    **MIT
  • 9:45 - 10:00 am Pacific - T1B.4. Uniformly Accurate Electrostatic Layered Medium Green’s Function Approximation via Scattered Field Formulation [127] (Student competition)
    Xinbo Li, Vladimir Okhmatovski
    University of Manitoba
  • 10:00 -10:20 am Pacific - Live Q&A2
    Panel of Presenters

10:20 - 10:30 am Pacific
Break

10:30 - 11:20 am Pacific
Tutorial III
Moderator:
Sweagato Chakraborty, Mentor
Power Delivery Architectures for Next Generation Microprocessors
Kaladhar Radhakrishnan
Intel
11:20 - 11:30 am Pacific
Live Q&A1
10:30 - 11:20 am Pacific
Tutorial IV
Moderator:
Junyan Tang, IBM
Analysis of Direct-to-Package 112G Channels
Michael Rowlands
Amphenol
11:20 - 11:30 am Pacific
Live Q&A2
11:30 am - 12:00 pm Pacific
IEEE EPS TC-EDMS Presentation
Moderator:
Dale Becker, IBM
  • TC-EDMS Packaging Benchmarks Committee Progress Report 2020
    Fei Guo*, Ali Yilmaz+
    *AMD, +UT Austin
12:00 - 12:50 pm Pacific
Session T2A - 3D Interconnects
Session Chair:
Marco Kassis, Cadence

  • 12:00 - 12:15 pm Pacific - T2A.1. 3D Integration of Ka-band RFIC by Inductive Inter-chip Wireless Communication Using Figure-8 Coils [60] (Student competition)
    Masahiro Usui+, Kota Shiba*, Mototsugu Hamada*, Tadahiro Kuroda*
    *The University of Tokyo,
    +Keio University
  • 12:15 - 12:30 pm Pacific - T2A.2. Estimating Per-Unit-Length Resistance Parameter in Emerging Copper-Graphene Hybrid Interconnects via Prior Knowledge based Accelerated Neural Networks [98] (Student competition)
    Somesh Kumar*, Sourajeet Roy+, B K Kaushik +, Ramachandra Achar**, Rohit Sharma++, Rahul Kumar++, Likith Narayan S S+
    *ABV-Indian Institute of Information Technology & Management,
    +IIT Roorkee,
    **Carleton Univeristy,
    ++IIT Ropar
  • 12:30 - 12:50 pm Pacific - Live Q&A1
    Panel of Presenters
12:00 - 12:50 pm Pacific
Session T2B - Measurements I
Session Chair:
Ming Yi, Nvidia

  • 12:00 - 12:15 pm Pacific - T2B.1. A Review of 90 Degree Corner Design for High-Speed Digital and mmWave Applications [29]
    Heidi Barnes+, Giovanni Bianchi*, Jose Moreira
    *Advantest,
    +Keysight Technologies
  • 12:15 - 12:30 pm Pacific - T2B.2. Assessment of 2x Thru De-embedding Accuracy for Package Transmission Line DUTs [77]
    Stephen Smith, Zhichao Zhang, Kemal Aygun
    Intel Corporation
  • 12:30 - 12:50 pm Pacific - Live Q&A2
    Panel of Presenters

12:50 - 1:00 pm Pacific
Day 2 Wrap Up
8:00 - 9:00 am Pacific
Invited Presentation - Closing the Loop from Architecture to Post-Silicon for Signal and Power Integrity
(Live Q&A - 8:50 - 9:00 am Pacific)
Vaishnav Srinivas
Qualcomm
9:00 - 10:20 am Pacific
Session W1A - Signal and Thermal Integrity
Session Chair:
Pavel Roy Paladhi, IBM

  • 9:00 - 9:15 am Pacific - W1A.1. Accurate BGA Package Solder Joint Modeling for High Speed SerDes Interfaces [71]
    Jiwei Sun, Zhiguo Qian, Cemil S. Geyik, Kemal Aygun
    Intel Corporation
  • 9:15 - 9:30 am Pacific - W1A.2. Reinforcement Learning-based Auto-router considering Signal Integrity [110] (Student competition)
    Minsu Kim, Hyunwook Park, Seongguk Kim, Keeyoung Son, Subin Kim, Kyungjune Son, Seonguk Choi, Gapyeol Park, Joungho Kim
    KAIST
  • 9:30 - 9:45 am Pacific - W1A.3. Thermal Sensitivity of Dielectric Materials in High-Speed Designs [104] (Student competition)
    Sunil Pathania*, Bhyrav Mutnury+, Mallikarjun Vasa**, Vijender Kumar**, Sukumar Muthusamy**, Seema P K**, Rohit Sharma*
    *IIT-Ropar,
    +Dell
    **DellEMC
  • 9:45 - 10:00 am Pacific - W1A.4. A Tunable Neural Network based Decision Feed-back Equalizer model for High-speed Link Simulation [12] (Student competition)
    Thong Nguyen, Jose Schutt-Aine
    UIUC
  • 10:00 - 10:20 am Pacific - Live Q&A1
    Panel of Presenters
9:00 - 10:20 am Pacific
Session W1B - Novel Interconnects
Session Chair:
Rohit Sharma, IIT, Ropar

  • 9:00 - 9:15 am Pacific - W1B.1. Design, Simulation and Measurement of a Flexible Voltage-controlled Oscillator (VCO) Chip with Bending Radius [102]
    Seungtaek Jeong*, Seongsoo Lee*, Seokwoo Hong*, Boogyo Sim*, Hyunwook Park*, Subin Kim*, Youngwoo Kim*, Keeyeong Son*, Joungho Ki*, Jaehak Lee+, Junyeop Son+
    *KAIST
    +Korea Institute of Machinery & Materials
  • 9:15 - 9:30 am Pacific - W1B.2. Cost-Effective Implementation of Air Filled Waveguides on Printed Circuit Boards [52] (Student competition)
    Felix Sepaintner*, Andreas Scharl*, Johannes Jakob*, Florian Keck*, Kevin Kunze*, Franz Roehrl+, Werner Bogner*, Stefan Zorn+
    *Technische Hochschule Deggendorf,
    +Rohde & Schwarz
  • 9:30 - 9:45 am Pacific - W1B.3. A Transmission Line Coupler Component for direct B2B communications [66]
    Reiji Miura, Tadahiro Kuroda, Mototsugu Hamada
    The University of Tokyo
  • 9:45 - 10:00 am Pacific - W1B.4. Causal Transmission Line Geometry Optimization for Impedance Control in PCBs [85]
    Zachariah Peterson
    Northwest Engineering Solutions
  • 10:00 - 10:20 am Pacific - Live Q&A2
    Panel of Presenters

10:20 - 10:30 am Pacific
Break

10:30 - 11:20 am Pacific
Tutorial V
Moderator:
Swagato Chakraborty, Mentor
Graphene-Based Emerging Interconnects - From Physics-Based Deterministic SPICE Models to Uncertainty Quantification
Sourajeet Roy*, Rohit Sharma+
*IIT, Roorkee
+IIT, Ropar
11:20 - 11:30 am Pacific
Live Q&A


11:30 am - 12:50 pm Pacific
Session W2A - Jitter Noise in High-Speed Links
Session Chair:
Mohiuddin Mazumder, Intel

  • 11:30 - 11:45 am Pacific - W2A.1. Analysis of Power Supply Noise Induced Jitter of I/O Subsystems with Multiple Power Domains [114]
    Hyo-Soon Kang, Ashkan Hashemi, Guang Chen, Xiaoping Liu, Wendemagegnehu Beyene
    Intel
  • 11:45 am - 12:00 pm Pacific - W2A.2. An Inspection Based Method to Analyse Deterministic Noise in N-port Circuits [73] (Student competition)
    Vijender Kumar Sharma+, Jai Narayan Tripathi*, Hitesh Shrimali+
    *IIT Jodhpur,
    +IIT Mandi
  • 12:00 - 12:15 pm Pacific - W2A.3. Variational Inference approach to Jitter decomposition in High-speed Link [81] (Student competition)
    Bobi Shi, Thong Nguyen, Jose Schutt-Aine
    UIUC
  • 12:15 -12:30 pm Pacific - W2A.4. Energy-Area Aware Channel Design for Multi-Chip Interfaces [123]
    Muhammad Waqas Chaudhary*, Andy Heinig*, Bhaskar Choubey+
    *Fraunhofer Institute,
    +Siegen University
  • 12:30 - 12:50 pm Pacific - Live Q&A1
    Panel of Presenters


10:30 - 11:30 am Pacific
Live Virtual Booths





11:30 am - 12:50 pm Pacific
Session W2B - Measurements II
Session Chair:
Heidi Barnes, Keysight

  • 11:30 - 11:45 am Pacific - W2B.1. Determine Socket’s Inductance and Contact Resistance by Using PRF Method [63]
    Tao Wang*, Jun Fan+
    *Qualcomm
    +MST
  • 11:45 am - 12:00 pm Pacific - W2B.2. Dual Sided High Frequency Measurement of Microelectronic Packages [48]
    Sean Christ, Ahmet Durgun, Kemal Aygun, Michael Hill
    Intel
  • 12:00 - 12:15 pm Pacific - W2B.3. SI Model to Hardware Correlation on a 44Gb/s HLGA Socket Connector [129]
    Pavel Roy Paladhi+, Yanyan Zhang+, Junyan Tang+, Daniel Rodriguez+, Jose Hejase*, Sungjun Chun+, Wiren Becker+, Brian Beaman+, Daniel Dreps+,
    *Nvidia,
    +IBM
  • 12:30 - 12:50 pm Pacific - Live Q&A2
    Panel of Presenters

12:50 - 1:00 pm Pacific
Conference Wrap-up (Live)