Return26th Conference on Electrical Performance of Electronic Packages and Systems, San Jose, CA - October 15-18 2017 - Preliminary Program

Advance Program

Sunday, October 15, 2017 Monday, October 16, 2017 Tuesday, October 17, 2017 Wednesday, October 18, 2017

1:00 - 2:30
Tutorial I
  • Statistical Link Modeling
    Wendem Beyene
    Rambus

2:30 - 3:00
Break

3:00 - 4:30
Tutorial II
  • ADC Base Links
    Sam Palermo
    Texas A&M

4:30 - 5:30
Tutorial III
  • 5G mmWave Packaging and Integration
    Kevin Gu
    IBM

8:00 - 8:15
Opening Remarks
8:15 - 9:00
Keynote Address
  • Machine Intelligence
    Winfried Wilke
    IBM
9:00 - 10:00
Session M-I: Power Integrity
  • M-I.1. Platform PI-PD Co-design and Validation for Power Efficient HSIO Interfaces (13)
    Xingjian Kinger Cai, Sze Geat Pang, Jimmy Huat Since Huang, Yan Li, Steven Yun Ji
    Intel
  • M-I.2. Distributed Sinusoidal Resonant Converter with High Step-Down Ratio (20)
    Eby Friedman1, Xin Li2, Gregory Sizikov2, Kan Xu1, Boris Vaisband1
    1University of Rochester,
    2Google
  • M-I.3. Output Impedance Design of Distributed Domains with High Frequency Voltage Regulators (86)
    Amit K. Jain, Chin Lee kuan, Sameer Shekhar
    Intel

10:00 - 10:30
Coffee Break

10:30 - 11:50
Session M-II: High-Speed Links
  • M-II.1. Per-bit Equalization Approach for Multi-Level Signal in High-Speed Design (73)
    Jiayi He1, Han Deng1, Nana Dikhaminjia1, Mikheil Tsiklauri1, James Drewniak1, Arun Chada2
    1MS&T
    2Dell
  • M-II.2. Substrate Integrated Common Mode Choke of EMI Filter for High Speed Serial Link (72)
    Boping Wu
    Huawei
  • M-II.3. Stitching Impedance Analysis of LPDDR Power Plane Split and Its Impact to Radio Frequency Interference (RFI) and Signal Integrity (SI) (70)
    Yingern Ho, Hao-Han Hsu, Jun Liao, Xingjian Kinger Cai
    Intel
  • M-II.4. Signal Slope Modulation Method for High Data Transfer Rates and Reducing Wiring Density in High-Speed Digital Systems (42)
    SMahesh Bohra, Jinwoo Choi, Yanyan Zhang
    IBM

11:50 - 1:20
Lunch Break

1:20 - 2:40
Session M-III: Signal Integrity
  • M-III.1. A Simple Method to Improve Signal Integrity of Electrostatic Discharge Protection Devices (64)
    Yang-Chih Huang, Chin-Yi Lin, Tzong-Lin Wu
    National Taiwan University
  • M-III.2. Effect of time delay skew on differential insertion loss in weak and strong coupled PCB traces (81)
    David Nozadze1, Amendra Koul1, Kartheek Nalla1, Mike Sapozhnikov1, Victor Khilkevich2
    1Cisco,
    2MS&T
  • M-III.3. Accurate and Efficient Impedance Matching Method in the Presence of On-board and SMT Parasitic Components (21)
    Tao Wang, Tim Michalka, Gerardo Romo Luevano
    Qualcomm
  • M-III.4. A Super Broadband DGS-based Common-mode Filter with a Compact Dimension (24)
    Po-Jui Li, Tzong-Lin Wu
    National Taiwan University

2:40 - 3:10
Coffee Break

3:10 - 4:10
Session M-IV - Electromagnetics
  • M-IV.1. Acceleration of Shielding Effectiveness Analysis Using Stable FDTD Subgridding (44)
    Fadime Bekmambetova, Xinyue Zhang, Piero Triverio
    University of Toronto
  • M-IV.2. Discontinuous Galerkin Time-Domain Analysis of Power/Ground Plate Pairs with Wave Port Excitation (32)
    Ping Li1, LiJun Jiang1, Hakan Bagci2
    1University of Hong Kong
    2KAUST
  • M-IV.3. Full-Wave Electromagnetic Characterization of 3D Interconnects Using a Surface Integral Formulation (62)
    Shunchuan Yang, Sean Hum, Piero Triverio, Utkarsh R. Patel, Shashwat Sharma
    University of Toronto

4:10 - 6:00
Session M-V: Poster Session
  • M-V.1. Interpolating Inductance Coupling Effects for Package and PCB Simulation (7)
    Thiel Werner, Xu Xin, Bracken J. Eric
    Ansys
  • M-V.2. An Indirect Measurement Method for S-Parameters which is based on Reduction to Eigenvalue Problem (8)
    Noboru Maeda1, Shinji Fukui1, Toshikazu Sekine2, Yasuhiro Takahashi2
    1Soken, Inc.,
    2Gifu University
  • M-V.3. EMI Radiation Physics Using Generalized Characteristic Mode (GCM) Analysis with Loss for Practical Structures (9)
    Xu Wang2, Ying S. Cao1, Lijun Jiang3, Albert Ruehli1, Shiquan He2, Huapeng Zhao2, Jun Hu2, Jun Fan1, Yansheng Wang1, James Drewniak1
    1MS&T
    2UEST,
    3University of Hong Kong
  • M-V.4. Impact of RE DCD in NAND Flash SI Simulation (12)
    Sayed Mobin, Arkady Katz, Balaji Raghunathan
    Western Digital
  • M-V.5. Suppression of Radiated Electromagnetic Emissions Using Absorbing Frequency Selective Surfaces (16)
    Ramesh Abhari, Ali Khoshniat
    Santa Clara University
  • M-V.6. Design Optimization of a Planar Spiral Inductor Using Space Mapping (18)
    Felipe de J. Leal-Romo1, Marisol Cabrera-Gomez1, Jose E. Rayas-Sanchez2, Daniel M. Garcia-Mora1
    1Intel Guadalajara
    2The Jesuit University of Guadalajara
  • M-V.7. Investigation of the Radiation Mechanism for High-Speed Connectors (23)
    Ying S. Cao1, Xu Wang2, Lijun Jiang2, Albert Ruehli1, Shiquan He2, Huapeng Zhao2, Jun Hu2, Jun Fan1, James Drewniak1
    1MS&T,
    2UEST,
    2The University of Hong Kong
  • M-V.8. Field-Circuit Coextraction of Systems with Interconnects and Circuit Components (26)
    Xiande Cao, Kaiyu Mao, Jian Liu, Yingxin Sun, Anyu Kuo
    Cadence
  • M-V.9. Analytical evaluation of partial inductances with retardation (29)
    Antonini Giulio1, Ruehli Albert2, Lombardi Luigi1
    1University of l'Aquila,
    2MS&T
  • M-V.10. Signal Integrity Analysis of High-Speed Board-to-Board Floating Connectors for Automotive Systems (34)
    Shinyoung Park1, Hyesoo Kim1, Jonghoon Kim1, Joungho Kim1, Unho Kim2, Jungmin Park2, Yuckhwan Jeon2
    1KAIST,
    2KET
  • M-V.11. Maximum Power Specification Management feature in Intel Xeon CPUs (36)
    Nazar Haider, Aman Sewani
    Intel
  • M-V.12. Evaluation of Concatenation Techniques for State-Space Interconnect Macromodels (50)
    Christian Schuster1, Luis Ernesto Carrera-Retana2, Renato Rimolo-Donadio2
    1Hamburg University of Technology,
    2Instituto Tecnologico de Costa Rica
  • M-V.13. Via Optimization for Next Generation Speeds (52)
    Siang Chen1, Tzong-Lin Wu1, Carol Chen2, Chun-Lin Liao2, James Chen2, Bhyrav Mutnury2
    1National Taiwan University, 2Dell
  • M-V.14. Inductance Model of the Decoupling Capacitors Including the Local Environment (56)
    Tamar Makharashvili, Ying Cao, Albert Ruehli, James Drewniak, Daryl Beetner
    MS&T
  • M-V.15. Boosting Off-chip Interconnects through Chip-to-Chip Capacitive Coupled Communication (58)
    Xiang Zhang, Chung-Kuan Cheng, Dongwon Park UCSD
  • M-V.16. Noise Based Rail Isolation Determination in Spatially Distributed IVR PDNs (65)
    Chin Lee Kuan , Amit K. Jain, Sameer Shekhar, Sanjiv C. Soman
    Intel
  • M-V.17. Cost Function Impact on S-Parameter Optimization Space (68)
    Daniel de Araujo, James Pingenot
    Mentor
  • M-V.18. Sensitivity of NRZ and PAM4 signaling schemes to Channel Insertion Loss Deviation (71)
    Giorgi Maghlakelidze, Santhosh Ranga Chavalla, Nana Dikhaminjia, James Drewniak
    MS&T
  • M-V.19. Effect of NEXT Coupling in Close Proximity to Receiver of 25Gb/s Bus (75)
    Pavel Roy Paladhi, Jose Hejase, Nam Pham, Ghadir Gholami, Prasanna Jayaraman2, Megan Nguyen, Glen Wiedemeier, Daniel Dreps
    IBM
  • M-V.20. DC Blocking Capacitor Interfacing for High Speed Communication Buses (77)
    Matthew Richardson, Junyan Tang, Jose Hejase, Daniel Dreps, Wiren Becker, Young Kwark
    IBM
  • M-V.21. Embeded Filtering in PCB Integrated Ultra High Speed Dielectric Waveguides Using Photonic Band Gap Structures (78)
    Joshua Myers, Jose Hejase, Junyan Tang, Daniel Dreps
    IBM
  • M-V.22. Reduced Pin Command and Address Bus for LPDDR4x Using Equalization Technique (82)
    Jun Liao, Konika Ganguly, Roman Melster, Jennifer Duong, Stephen P Christianson, Xingjian Kinger Cai
    Intel
  • M-V.23. A Parallel Iterative Layered-Medium Integral-Equation Solver for Electromagnetic Analysis of Electronic Packages (83)
    Chang Liu 1, Kemal Aygün2, Henning Braunisch2, Vladimir Okhmatovski2, Ali Yılmaz1
    1UT Austin,
    2University of Manitoba
  • M-V.24. A Hybrid Land Grid Array Connector Design for Achieving Higher Signalling Data Rates (85)
    Jose Hejase, Sungjun Chun, Wiren Becker, Daniel Dreps, Brian Beaman
    IBM
  • M-V.25. Matrix Formulations and GPU Acceleration for High-Speed Digital Link Simulations (102)
    Arash Zargaran-Yazd, Sunil Sudhakaran
    NVIDIA

7:00 - 9:00
TPC Meeting

8:00 - 8:45
Keynote Address
Chair:
Paul Franzon, NCSU
  • Exascale Computing
    John Shalf
    Lawrence Livermore Labs
8:45 - 10:25
Session T-I: Link Modeling
  • T-I.1. System-level Coexistence Impact of USB Type-C and Type-A Connectors with WiFi Radio (76)
    Jaejin Lee, Hao-han Hsu, Chung-hao Chen, Xiang Li, Xingjian Kinger Cai
    Intel
  • T-I.2. SAS 4.0 (22.5Gbps) Challenges for Server Platforms (92)
    Vijender Kumar, Gowri Anand, Sanjay Kumar, Mallikarjun Vasa, Douglas Wallace
    Dell
  • T-I.3. LPDDR4X (3732 Mbps) DBI Impact on SI/PI and Power (2)
    Sunil Gupta
    Qualcomm
  • T-I.4. Modeling of DDR5 Signaling from Jitter Sequences to Accurate Bit Error (BER) Analysis (41)
    Alaeddin Aydiner, Yunhui Chu, Oleg Mikulchenko, Jin Yan, Robert Friar, Ellen Yan Fu
    Intel
  • T-I.5. A New Approach to Mitigate PCI Express Gen4 Crosstalk from Sideband Signals in Connectors (79)
    Yaping, Zhou, Wenjun Shi, Sudhakaran Sunil
    Nvidia

10:25 - 10:45
Morning Coffee Break

10:45 - 12:45
Session T-II: Advanced Characterization of Interconnects
  • T-II.1. Signal Integrity Analysis of Machine Pressed Coaxial Connector for Automotive System (57)
    Dong-Hyun Kim1, Hyunsuk Lee1, Jonghoon Kim1, Jung-Min Park2, Un-ho Kim2, Kun-ho Kim2, Yeok-Hwan Jeon2, Hyeok-Cheol Kwon2, Hoon Kim2, Maeng-ki Song2, Joungho Kim1
    1KAIST 2 Korea Electric Terminal Co,
  • T-II.2. Signal Via Coupling Effects Caused by Partially Broken High Frequency Signal Return (60)
    Thomas-Michael Winkel
    IBM Deutschland
  • T-II.3. Verifying the Accuracy of 2X-Thru De-Embedding for Unsymmetrical Test Fixtures (84)
    Heidi Barnes, Jose Moreira
    Keysight
  • T-II.4. Improve mm-Wave Measurement Repeatability and Accuracy by Increasing Coaxial Connector Pin Gap (54)
    Ken Wong
    Keysight
  • T-II.5. Causal Version of Conductor Roughness Models and its Effect on Characteristics of Transmission Lines (4)
    Vladimir Dmitriev-Zdorov1, Lambert Simonovich2
    1Mentor Graphics,
    2Lamsim Enterprises Inc
  • T-II.6. Unified approach to interconnect conductor surface roughness modelling (15)
    Yuriy Shlepnev
    Simberian Inc.

12:45 - 1:45
Lunch Break

12:45 - 1:45
TPC Meeting

1:45 - 3:25
Session T-III: Macromodeling
  • T-III.1. Bivariate macromodeling with guaranteed uniform stability and passivity (22)
    Stefano Grivet-Talocia
    Politecnico di Torino
  • T-III.2. MIP: Moment-Based Interpolation Projection for Parameterized Reduced Models of the DC Operating Point in Nonlinear Circuits (45)
    Michel Nakhla1, Qi Sun1, Ram Achar1, Ye Tao1, Behzad Nouri1, Emad Gad2
    1Carleton University,
    2University of Ottawa
  • T-III.3. Toward Virtual Prototyping of Power Electronics: Model Order Reduction for Tight-Coupled Electro-Thermal Simulation (67)
    Quan Chen, Ngai Wong
    University of Hong Kong
  • T-III.4. FastAAA: A fast rational-function fitter (80)
    Amit Hochman
    Ansys
  • T-III.5. A Novel Tensor-Based Model Compression Method via Tucker and Tensor Train Decompositions (43)
    Cong Chen, Kim Batselier, Ngai Wong
    University of Hong Kong

3:25 - 3:50
Afternoon Break

3:50 - 4:50
Session T-IV: Stochastic Modeling
  • T-IV.1. Adaptive Wavelet Stochastic Collocation for Resonant Transmission Line Circuits (51)
    Alan Yang, Xu Chen, Andreas Cangellaris, Jose Schutt-Aine
    University of Illinois
  • T-IV.2. A Novel Stochastic Wave Model Statistically Replicating Reverberation Chambers (87)
    Shen Lin, Zhen Peng
    University of New Mexico
  • T-IV.3. Mixed Epistemic-Aleatory Uncertainty Quantification using Reduced Dimensional Polynomial Chaos and Parametric ANOVA (31)
    Sourajeet Roy, Aditi Prasad
    Colorado State University

4:50 - 6:10
Session T-V: Advanced Modeling
  • T-V.1. Analysis of Integrated Metal Seal Ring Resonance (5)
    Maxime Jacques1, David Denis2, Stephane Bouvier2, Alireza Samani1, Faycal Mounaim2, David Plant1
    1McGill University,
    2Murata
  • T-V.2. Chip/Package Co-Analysis and Inductance Extraction for Fan-Out Wafer-Level-Packaging (74)
    Yarui Peng1, Dusan Petranovic2, Sung Kyu Lim3
    1University of Arkansas,
    2Mentor Graphics,
    3Georgia Tech
  • T-V.3. Computation of the X-Parameters of Multi-Tone Circuits using Multipoint Moment Expansion(96)
    Marco Kassis1, Dani Tannir2, Raffi Toukhtarian1, Roni Khazaka1
    1McGill University,
    2Lebanese American University
  • T-V.4. The Accuracy of Port Connections between Layers in Printed Circuit Board (53)
    Albert Ruehli1, Stephen Scearce2, James Drewniak1, Chenxi Huang3, Siqi Bai1
    1MS&T,
    2Cisco

9:00 - 10:20
Session W-I: Machine Learning I
  • W-I.1. Black Box Optimization of 3D Integrated Systems using Machine Learning (10)
    Hakki Torun, Madhavan Swaminathan
    Georgia Tech
  • W-I.2. A Novel Use of Deep Learning to Optimize Solution Space Exploration for Signal Integrity Analysis (11)
    Mruganka Kashyap1, Kumar Keshavan2, Ambrish Varma2
    1UCSD,
    2Cadence
  • W-I.3. A Method for Creating Behavioral Models of Oscillators Using Augmented Neural Networks (27)
    Madhavan Swaminathan1, Chuanyi Ji1, David White2, Huan Yu1
    1Georgia Tech,
    2Cadence
  • W-I.4. Verilog-A Compatible Recurrent Neural Network Model for Transient Circuit Simulation (69)
    Zaichen Chen, Maxim Raginsky, Elyse Rosenbaum
    University of Illinois

10:20 - 11:10
Morning Coffee Break

11:10 - 12:10
Session W-II: Machine Learning II
  • W-II.1. Using Deep Neural Networks to Model Nonlinear Circuit Blocks in Wireline Links (40)
    Sunil Sudhakaran, Arash Zargaran-Yazd
    NVIDIA
  • W-II.2. Reduced-Order Modeling of high-Speed Channels Using Machine Learning Techniques: Partitional and Hierarchical Clusterings (97)
    Wendem Beyene
    Rambus
  • W-II.3. High-Speed Channel Modeling with Deep Neural Network for Signal Integrity Analysis (55)
    Ken Wu1, Zhiping Yang1, Tianjian Lu1, Ju Sun2
    1Google,
    2Stanford University

12:10 - 12:20
Closing Remarks

1:00 - 4:00
Workshop on Machine Learning for Hardware Design