Return31st Conference on Electrical Performance of Electronic Packages and Systems,
San Jose, CA - October 9-12 2022 - Advance Program
Advance Program
Sunday, October 9, 2022
Monday, October 10, 2022
Tuesday, October 11, 2022
Wednesday, October 12, 2022
8:00 - 4:00
Tutorials
Tutorial I - TBA (8:00-9:00)
Mohiuddin Mazumder,
Intel
Tutorial II - Design and Verification of DDR5 Channels (9:00-10:00)
Kirk Fabbri
Siemens EDA
10:00 - 11:00
Break
Tutorial III - TBA (10:10 - 11:10)
Pegah Alavi
Keysight
Tutorial IV - Fundamentals of machine learning methodologies for the design of modern RF and microwave systems (11:10 - 12:10)
Domenico Spina
Ghent University - imec
12:10 - 1:30
Lunch Break
Tutorial V - TBA (1:30 - 2:30)
Sourajeet Roy1, Rohit Sharma2
1IIT, Roorkee, 2IIT, Ropar
Tutorial VI - Integral equation methods for the electromagnetic analysis of interconnect networks: state of the art and open challenges (2:30 - 3:30)
Piero Triverio
University of Toronto
Tutorial VII - Uncertainty Quantification in Electronic Designs: From Polynomial Chaos Expansion to Gaussian Processes (3:30 - 4:30)
Paolo Manfredi
Politecnico di Torino
Tutorial VIII - Intelligent High Speed Structure Optimization (4:30 - 5:30)
Suomin Cui, Davi Correia
Cadence
7:00 - 7:50
Breakfast
7:50 - 8:00
Opening Remarks
8:00 - 9:00
Keynote I
Chair:
Zhen Peng, University of Illinois at Urbana-Champaign
Packaging trends and challenges for next generation of high-speed interconnects
Vishnu Balan
Nvidia
9:00 - 10:00
Session M-I: High Speed Link
Chair:
Jose Hejase, Nvidia
M-I.1. Advanced Fly-By Routing Topology for Gbps DDR5 Systems (9)
Shinyoung Park
Rambus
M-I.2. Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm (37)
Chulhee Cho
Samsung Electronics
M-I.3. Hardware Verification of Via Crosstalk Cancellation for Differential BGA-to-BGA Links (49)
Katharina Scharff
IBM Deutschland
10:00 - 10:20
Coffee Break
10:20 - 12:00
Session M-II: Power Integrity
Chair:
Stefano Grivet-Talocia, Politecnico di Torino
M-II.1. Towards Accelerated Transient Solvers for Full System Power Integrity Verification (56)
Antonio Carlucci
Politecnico di Torino
M-II.2. Inverse Design of Embedded Inductor with Hierarchical Invertible Neural Transport Net (81)
Oluwaseyi Akinwande
Georgia Institute of Technology
M-II.3. Reinforcement Learning for the Optimization of Power Plane Designs in Power Delivery Networks (29)
Seunghyup Han
Georgia Institute of Technology
M-II.4. Network Model Compensation For Single-Point Measurements Of Multi-Pin Devices When Using Non-Invasive Current Estimation (5)
Chad Smutzer
Mayo Clinic
M-II.5. Efficient Modeling of Random Jitter Due to Stochastic Power Supply Noise in CMOS Inverters (89)
Ahsan Javaid
Carleton University
12:00 - 12:45
Lunch Break
12:45 - 1:30
TC EDMS Meeting
1:30 - 3:00
Heterogeneous Integration Workshop
Chairs:
Jose Schutt-Aine, University of Illinois at Urbana-Champaign
Bill Chen, ASE Group
Kemal Aygun, Intel
3:00 - 3:20
Coffee Break
3:20 - 5:00
Session M-III: Poster Session
Chairs:
Sourajeet Roy, IIT, Roorkee
Matthew Doyle, IBM
M-III.1. Advanced Measurement and Simulation Approach for DDR5 On-chip SI/PI with the Probing Package (22)
WonSuk Choi
Samsung Electronics
M-III.2. Codimensional Optimization of Differential Via Padstacks (75)
Daniel De Araujo
Siemens EDA
M-III.3. Distributed PDN Modeling Approach for Accurate Jitter Estimation in High-Speed NAND Flash Memory (3)
Sayed Mobin
Western Digital
M-III.4. Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM (40)
Hyunwook Park
KAIST
M-III.5. Crosstalk Analysis for PCIe 6.0 (PAM4) Under Different Transmitter Conditions (27)
Fabio Ruiz
Intel
M-III.6. Impedance and Cost based PDN Decoupling Optimization using Reinforcement Learning (57)
Allan Sanchez-Masis
Intel
M-III.7. Memory Speed Enhancement via SI/PI Optimization in Constrained Tablet Designs (43)
Simon See
Intel
M-III.8. Intra-pair Skew Impact Analysis of High Speed Cables for HDMI Interface (76)
Boogyo Sim
KAIST
M-III.9. NEXT Effect in Pin-area Routing at Receiver End from Via to Trace Coupling in a 32 Gb/s Channel (88)
Pavel Roy Paladhi
IBM Corporation
3:00 - 5:00
Sponsor Booths
7:00 - 7:50
Breakfast
7:50 - 8:00
Day 3 Welcome
8:00 - 9:00
Keynote II
Chair:
Swagato Chakraborty, Siemens EDA
From Micro-Watts to Terawatts, the Road to Compute Energy Efficiency
Tawfik Rahal-Arabi
AMD
8:00 - 9:00
Session T-I: Signal and Thermal Integrity
Chairs:
Xu Chen, University of Illinois at Urbana-Champaign
T-I.1. Realistic Stripline Corner Modeling Using Surrogate Model and Topographic Fitting (58) (Student Competition)
Andrew Page
IBM Corporation
T-I.2. Fast LDO Simulations via Parameter-Varying Linearized Macromodels (54)
Tommaso Bradde
Politecnico di Torino
T-I.3. Signal Integrity and Power Leakage Optimization for 3D X-Point Memory Operation using Reinforcement Learning (6)
Kyungjune Son
KAIST
10:00 - 10:20
Coffee Break
10:20 - 12:00
Session T-II: Applied Electromagnetics
Chairs:
Piero Triverio, University of Toronto
T-II.1. Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method (32)
Dries Bosman
Ghent University
T-II.2. CISPR 25 Radiated Emission Simulation and Measurement Correlation of an Automotive Reinforced Isolated Switch Driver (42)
Jie Chen
Texas Instruments
T-II.3. Deterministic Policy-based Reinforcement Learning Method for Optimization method (39)
Daehwan Lho
KAIST
T-II.4. An Efficient Methodology to Parse and Mesh Large Interconnect Layouts for Electromagnetic Analysis (72)
Piero Triverio
University of Toronto
T-II.5. Novel Closed-Form 2-D Green's Function of Shielded Layered Media And Its Use in Transmission Lines Inductance Extractin (69)
Vladimir Okhmatovski
University of Manitoba
12:00 - 1:20
Lunch Break
12:00 - 1:30
TPC Meeting
1:30 - 3:00
Packaging Benchmark Workshop - Part 1
Chairs:
Vladimir Ohkmatovski, University of Manitoba
Heidi Barnes, Keysight
3:00 - 3:20
Coffee Break
3:20 - 5:00
Packaging Benchmark Workshop - Part 2
Chairs:
Vladimir Ohkmatovski, University of Manitoba
Heidi Barnes, Keysight
5:00 - 5:50
Sponsors Student Recruiting Event
7:00 - 9:00
Banquet
7:00 - 7:50
Breakfast
7:50 - 8:00
Day 4 Welcome
8:00 - 9:00
Keynote III
Chair:
Zhen Peng, University of Illinois Urbana-Champaign
TBA
Alberto Valdes-Garcia
IBM Research
9:00 - 9:40
Session W-I: Advanced CAD
Chairs:
Pavel Roy Paladhi, IBM Corporation
W-I.1. An Efficient Parallel Electromagnetic Solver for Extracting Scattering Parameters from Large Electrical Interconnects With Many Ports (70)
Damian Marek
University of Toronto
W-I.2. A Transfer Learning Approach to Expedite Training of Artificial Neural Networks for Variability-Aware Signal Integrity Analysis of MWCNT Interconnects (62)
Sourajeet Roy
IIT, Roorkee
9:40 - 10:00
Session W-II: Measurements
Chair:
Rohit Sharma, IIT, Ropar
W-II.1. An Improved Methodology for High Frequency Socket Performance Characterization (48)
Saikat Mondal
Intel
10:00 - 10:20
Coffee Break
10:20 - 11:00
Session W-III: DDR Interfaces
Chairs:
Rohit Sharma, IIT, Ropar
W-III.1. On-Dual In-line Memory Module (DIMM) Low- Pass Filter (LPF) using Via Stubs for Enhancing Signal Integrity (46)
Seungjin Lee
Samsung Electronics
W-III.2. A Novel Differential Signal Routing Metohd for High-Speed and Large-Capacity DDR5 Dual-In-Line Memory Module (20)
Yun-Ho Lee
Samsung Electronics
11:00 - 12:40
Session W-IV: RF Packages
Chair:
Rajen Murugan, Texas Instruments
W-IV.1. Improvement of Radiation Characteristics of a 300-GHz On-Chip Patch Antenna with Epoxy Mold Compound (EMC) Encapsulation (48)
Harshpreet Singh Bakshi
Texas Instruments
W-IV.2. Design and Optimization of High-Speed Digital Bus Over RF Channel (84)