Return31st Conference on Electrical Performance of Electronic Packages and Systems, San Jose, CA - October 9-12 2022 - Final Program

Final Program

Sunday, October 9, 2022 Monday, October 10, 2022 Tuesday, October 11, 2022 Wednesday, October 12, 2022

8:00 - 4:00
  • Tutorial I - Data Rate Scaling for Backwards Compatible PCIe Interconnect (8:00-9:00)
    Mohiuddin Mazumder,
  • Tutorial II - Design and Verification of DDR5 Channels (9:00-10:00)
    Kirk Fabbri
    Siemens EDA

  • 10:00 - 10:10

  • Tutorial III - High Speed SERDES and specifically PCIe6's design challenges with PAM4 signaling (10:10 - 11:10)
    Pegah Alavi
  • Tutorial IV - Fundamentals of machine learning methodologies for the design of modern RF and microwave systems (11:10 - 12:10)
    Domenico Spina
    Ghent University - imec

  • 12:10 - 1:30
    Lunch Break

  • Tutorial V - Recent advances in electro-thermal co-design for signal integrity analysis of next generation interconnects and packages (1:30 - 2:30)
    Sourajeet Roy1, Rohit Sharma2
    1Indian Institute of Technology, Roorkee, 2Indian Institute of Technology, Ropar
  • Tutorial VI - Integral equation methods for the electromagnetic analysis of interconnect networks: state of the art and open challenges (2:30 - 3:30)
    Piero Triverio
    University of Toronto
  • Tutorial VII - Uncertainty Quantification in Electronic Designs: From Polynomial Chaos to Gaussian Processes (3:30 - 4:30)
    Paolo Manfredi
    Politecnico di Torino
  • Tutorial VIII - Intelligent High Speed Structure Optimization (4:30 - 5:30)
    Suomin Cui, Davi Correia

7:00 - 7:50

7:50 - 8:00
Opening Remarks
8:00 - 9:00
Keynote I
Zhen Peng, University of Illinois Urbana-Champaign
  • Packaging trends and challenges for next generation of high-speed interconnects
    Vishnu Balan

9:00 - 10:00
Session M-I: High Speed Link
Jose Hejase, Nvidia
  • M-I.1. Advanced Fly-By Routing Topology for Gbps DDR5 Systems (9)
    Shinyoung Park, Vinod Arjun Huddar
  • M-I.2. Differential Via Optimization for PCIe Gen5 Channel based on Particle Swarm Optimization Algorithm (37)
    Chulhee Cho, Kwangho Kim, Manho Lee, Jaeyoung Shin, Sungjin Yoon, Youngjae Lee, Chayoung Song, Wooshin Choi, Myoungbo Kwak, Youngdon Choi, Jung-Hwan Choi, Hyungjong Ko
    Samsung Electronics
  • M-I.3. Hardware Verification of Via Crosstalk Cancellation for Differential BGA-to-BGA Links (49)
    Katharina Scharff1, Xiaomin Duan1, Matteo Cocchini2, Hung Nguyen2, Nicole Selezinski3, Dierk Kaller1, Hubert Harrer1
    1IBM Deutschland Research & Development GmbH

    2IBM Corporation

    3Hamburg University of Technology

10:00 - 10:20
Coffee Break

10:20 - 12:00
Session M-II: Power Integrity
Stefano Grivet-Talocia, Politecnico di Torino
  • M-II.1. Inverse Design of Embedded Inductor with Hierarchical Invertible Neural Transport Net (81)
    Oluwaseyi Akinwande, Osama Waqar Bhatti, Madhavan Swaminathan
    Georgia Institute of Technology
  • M-II.2. Towards Accelerated Transient Solvers for Full System Power Integrity Verification (56) (Student Competition)
    Antonio Carlucci1, Stefano Grivet-Talocia1, Scott Mongrain2, Sid Kulasekaran2, Kaladhar Radhakrishnan2
    1Politecnico di Torino

    2Intel Corporation

  • M-II.3. Reinforcement Learning for the Optimization of Power Plane Designs in Power Delivery Networks (29) (Student Competition)
    Seunghyup Han, Osama Waqar Bhatti, Madhavan Swaminathan
    Georgia Institute of Technology
  • M-II.4. Network Model Compensation For Single-Point Measurements Of Multi-Pin Devices When Using Non-Invasive Current Estimation (5)
    Chad Smutzer, Jordan Keuseman, Clifton Haider, Barry Gilbert
    Mayo Clinic - SPPDG
  • M-II.5. Efficient Modeling of Random Jitter Due to Stochastic Power Supply Noise in CMOS Inverters (85) (Student Competition)
    Ahsan Javaid1, Ramachandra Achar1, Jai Tripathi2
    1Carleton University

    2Indian Institute of Technology Jodhpur

12:00 - 12:45
Lunch Break

12:45 - 1:30
TC EDMS Meeting

1:30 - 3:20
Special Session: Co-Design for Chiplets
Jose Schutt-Aine, UIUC
Bill Chen, ASE Group
Kemal Aygun, Intel

3:20 - 5:00
Session M-III: Poster Session
Jose Hejase, Nvidia
Vladimir Ohkmatovski, University of Manitoba
  • M-III.1. Advanced Measurement and Simulation Approach for DDR5 On-chip SI/PI with the Probing Package (22)
    WonSuk Choi, SangKeun Kwak, Jaeseok Park, Jiyoung Do, Byeongseon Yun, Yoo-jeong Kwon, Dongyeop Kim, Kyudong Lee, Tae young Kim, Wonyoung Kim, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho
    Samsung Electronics
  • M-III.2. Codimensional Optimization of Differential Via Padstacks (75)
    Jiwoong Jeon1, Shivani Joshi1, Daniel de Araujo1, Bhyrav Mutnury2
    1Siemens EDA

    2Dell EMC

  • M-III.3. Distributed PDN Modeling Approach for Accurate Jitter Estimation in High-Speed NAND Flash Memory (3)
    Sayed Mobin, Pranav Balachander, Asha Sharma, Venkatesh Ramachandra
    Western Digital
  • M-III.4. Scalable Transformer Network-based Reinforcement Learning Method for PSIJ Optimization in HBM (40)
    Hyunwook Park1, Taein Shin1, Seongguk Kim1, Daehwan Lho1, Boogyo Sim1, Jinwook Song2, Kyubong Kong3, Joungho Kim1
    1Korea Advanced Institute of Science and Technology

    2Samsung Electronics

    3SK Hynix

  • M-III.5. Crosstalk Analysis for PCIe 6.0 (PAM4) Under Different Transmitter Conditions (27)
    Fabio A. Ruiz-Molina, Jingbo Li, Kai Xiao
  • M-III.6. Impedance and Cost based PDN Decoupling Optimization using Reinforcement Learning (57)
    Allan Sanchez-Masis, Sameer Shekhar
  • M-III.7. Memory Speed Enhancement via SI/PI Optimization in Constrained Tablet Designs (43)
    Simon Chun Kit See, Asmah Truky, Gaurav Hada, Sameer Shekhar, Chandru Raman
  • M-III.8. Intra-pair Skew Impact Analysis of High Speed Cables for HDMI Interface (76) (Student Competition)
    Boogyo Sim1, Keunwoo Kim1, Taein Shin1, Hyunwook Park1, Seongguk Kim1, Daehwan Lho1, Keeyoung Son1, Kyubong Kong2, Seungtaek Jeong3, Seonguk Choi1, Jihun Kim1, Joungho Kim1
    1Korea Advanced Institute of Science and Technology

    2SK Hynix

    3Missouri University of Science and Technology

  • M-III.9. NEXT Effect in Pin-area Routing at Receiver End from Via to Trace Coupling in a 32 Gb/s Channel (88)
    Pavel Roy Paladhi, Yanyan Zhang, Xianbo Yang, Nam Pham, Megan Nguyen, Mahesh Bohra, Junyan Tang, Sungjun Chun, Joshua Myers, Wiren Becker, Daniel Dreps
    IBM Corporation

3:20 - 5:00
Sponsor Booths

7:00 - 7:50

7:50 - 8:00
Day 3 Welcome
8:00 - 9:00
Keynote II
Swagato Chakraborty, Siemens EDA
  • From Micro-Watts to Terawatts, the Road to Compute Energy Efficiency
    Tawfik Rahal-Arabi

8:00 - 9:00
Session T-I: Signal and Thermal Integrity
Xu Chen, University of Illinois Urbana-Champaign
  • T-I.1. Realistic Stripline Corner Modeling Using Surrogate Model and Topographic Fitting (58) (Student Competition)
    Andrew Page1, Matteo Cocchini1, Zhaoqing Chen1, Xu Chen2
    1IBM Corporation

    2University of Illinois Urbana-Champaign

  • T-I.2. Fast LDO Simulations via Parameter-Varying Linearized Macromodels (54)
    Tommaso Bradde, Stefano Grivet-Talocia
    Politecnico di Torino
  • T-I.3. Signal Integrity and Power Leakage Optimization for 3D X-Point Memory Operation using Reinforcement Learning (6) (Student Competition)
    Kyungjune Son1, Keunwoo Kim1, Gapyeol Park1, Daehwan Lho1, Hyunwook Park1, Boogyo Sim1, Taein Shin1, Joonsang Park1, Haeyeon Kim1, Kyubong Gong2, Joungho Kim1
    1Korea Advanced Institute of Science and Technology

    2SK Hynix

10:00 - 10:20
Coffee Break

10:20 - 12:00
Session T-II: Applied Electromagnetics
Piero Triverio, University of Toronto
  • T-II.1. Interconnect Modeling using a Surface Admittance Operator Derived with the Fokas Method (32) (Student Competition)
    Dries Bosman1, Martijn Huynen1, Daniel De Zutter1, Xiao Sun2, Nicolas Pantano2, Geert Van der Plas2, Eric Beyne2, Dries Vande Ginste1
    1Ghent University


  • T-II.2. CISPR 25 Radiated Emission Simulation and Measurement Correlation of an Automotive Reinforced Isolated Switch Driver (42)
    Jie Chen1, Rajen Murugan1, Sooping Saw1, Francisco Lauzurique1, John Broze1, Craig Greenberg1, Alex Triano1, Bibhu Nayak2, Harikiran Muniganti2, Joe Sivaswamy2, Dipanjan Gope2
    1Texas Instruments


  • T-II.3. Deterministic Policy-based Reinforcement Learning Method for Optimization method (39) (Student Competition)
    Daehwan Lho1, Hyunwook Park1, Keunwoo Kim1, Seongguk Kim1, Boogyo Sim1, Kyungjune Son1, Keeyoung Son1, Jihun Kim1, Seonguk Choi1, Joonsang Park1, Haeyeon Kim1, Kyubong Kong2, Joungho Kim1
    1Korea Advanced Institute of Science and Technology

    2SK Hynix

  • T-II.4. An Efficient Methodology to Parse and Mesh Large Interconnect Layouts for Electromagnetic Analysis (72) (Student Competition) (Benchmark Competition)
    Qinghao Zhang1, Ruoyi Xie1, Fei Guo2, Shashwat Sharma1, Damian Marek1, Piero Triverio1
    1University of Toronto


  • T-II.5. Novel Closed-Form 2-D Green's Function of Shielded Layered Media And Its Use in Transmission Lines Inductance Extractin (69)
    Shucheng Zheng, Vladimir Okhmatovski
    University of Manitoba

12:00 - 1:20
Lunch Break

12:00 - 1:30
TPC Meeting

1:30 - 3:00
Packaging Benchmark Workshop - Part 1
Vladimir Ohkmatovski, University of Manitoba
Heidi Barnes, Keysight

3:00 - 3:20
Coffee Break

3:20 - 5:00
Packaging Benchmark Workshop - Part 2
Vladimir Ohkmatovski, University of Manitoba
Heidi Barnes, Keysight

5:00 - 5:50
Sponsors Student Recruiting Event

7:00 - 9:00

7:00 - 7:50

7:50 - 8:00
Day 4 Welcome
8:00 - 9:00
Keynote III
Zhen Peng, University of Illinois Urbana-Champaign
  • Packaging and module integration as a catalyst for innovation in millimeter-wave systems
    Alberto Valdes-Garcia
    IBM Research

9:00 - 9:40
Session W-I: Advanced CAD
Paolo Manfredi, Politecnico di Torino
  • W-I.1. An Efficient Parallel Electromagnetic Solver for Extracting Scattering Parameters from Large Electrical Interconnects With Many Ports (70) (Student Competition) (Benchmark Competition)
    Damian Marek, Piero Triverio
    University of Toronto
  • W-I.2. A Transfer Learning Approach to Expedite Training of Artificial Neural Networks for Variability-Aware Signal Integrity Analysis of MWCNT Interconnects (62)
    Surila Guglani1, Km Dimple1, Avirup Dasgupta1, Rohit Sharma2, Brajesh Kaushik1, Sourajeet Roy1
    1Indian Institute of Technology, Roorkee

    2Indian Institute of Technology, Ropar

9:40 - 10:00
Session W-II: Measurements
Rohit Sharma, Indian Institute of Technology, Ropar
  • W-II.1. An Improved Methodology for High Frequency Socket Performance Characterization (90)
    Saikat Mondal, Dhanya Athreya, Emile Davies-Venn, Zhichao Zhang, Kemal Aygun

10:00 - 10:20
Coffee Break

10:20 - 11:00
Session W-III: DDR Interfaces
Rohit Sharma, Indian Institute of Technology, Ropar
  • W-III.1. On-Dual In-line Memory Module (DIMM) Low- Pass Filter (LPF) using Via Stubs for Enhancing Signal Integrity (46)
    Seungjin Lee, Jonghoon Kim, Jinseong Yun, Heejin Cho, Youngho Lee, Kyoungsun Kim, Sungjoo Park, Jeonghyeon Cho, Hoyoung Song
    Samsung Electronics
  • W-III.2. A Novel Differential Signal Routing Metohd for High-Speed and Large-Capacity DDR5 Dual-In-Line Memory Module (20)
    Yun-Ho Lee, Dongyeop Kim, SangKeun Kwak, Jeonghun Baek, Kyoungsun Kim, Sung Joo Park, Jeonghyeon Cho, Hoyoung Song
    Samsung Electronics

11:00 - 12:40
Session W-IV: RF Packages
Yaping Zhou Nvidia
  • W-IV.1. Improvement of Radiation Characteristics of a 300-GHz On-Chip Patch Antenna with Epoxy Mold Compound (EMC) Encapsulation (48)
    Harshpreet Singh Bakshi, Rajen Murugan, Sylvester Ankamah-Kusi
    Texas Instruments
  • W-IV.2. Design and Optimization of High-Speed Digital Bus Over RF Channel (84)
    Nikhita Baladari, Robert Wenzel
    NXP Semiconductors
  • W-IV.3. 2D Spectral Transposed Convolutional Neural Network for S-Parameter Predictions (73) (Student Competition)
    Yiliang Guo, Xingchen Li, Madhavan Swaminathan
    Georgia Institute of Technology
  • W-IV.4. Methods to Characterize Radiation Patterns of WR5 Band Integrated Antennas in a Flip-Chip Enhanced QFN Package (74) (Student Competition)
    Aditya Nitin Jogalekar1, Oscar Media1, Andrew Blanchard1, Rashaunda Henderson1, Mahadevan Iyer2, Hassan Ali3, Rajen Murugan3, Tony Tang4
    1The University of Texas at Dallas

    2Amkor Technologies

    3Texas Instruments

    4Astera Labs

  • W-IV.5. A Low EMI Board-to-board Connector Design for 5G mmWave and High-speed Signaling (47)
    Keunwoo Kim1, Junghyun Lee1, Seokwoo Hong1, Hyunwoo Kim1, Boogyo Sim1, Kyungjune Son1, Taein Shin1, Keeyoung Son1, Jinyoung Kim2, Kyubong Kong3, Joungho Kim1
    1Korea Advanced Institute of Science and Technology

    2Korea Electric Terminal (KET)

    3SK Hynix

12:40 - 12:55
Conference Wrap-up

12:55 - 2:00
Buffet Lunch