EPEPS 2020: San Jose, CA
IEEE
Tutorial II
Machine Learning for EDA in Packaging

Madhavan Swaminathan, Georgia Tech

The semiconductor industry has always been plagued by design re-spins often times attributable to the complexity of the designs that need to be taped out. As we move into the sub-10nm process nodes, as the interposer technologies begin to support sub-2um line geometries, as the designs become more analog in nature where parasitic effects become very critical, the room available for design errors will only decrease, thereby increasing the probability for design mistakes. Part of the reason for design re-spins in the past has been that simulation based design optimization techniques have had limited success due to the long design cycle times, often requiring designers to take short cuts. Can Machine Learning help alleviate this problem? In this tutorial I will start with the basics of machine learning to try and answer some fundamental questions often asked such as: i) What is Machine Learning (ML)?, ii) Is ML akin to curve fitting, iii) Does ML have predictive capabilities that always provides the right answer?, iv) What is so unique about ML for EDA as compared to say image recognition?, to name a few. I will then discuss the application of ML in the areas of behavioral modeling, optimization, prediction and uncertainty quantification with a focus on both the fundamental and advanced concepts. In particular these techniques will be applied to real world examples arising in 3DIC, Integrated Voltage Regulators (IVR), Wireless Power Transfer (WPT), sub-THz mmwave and Serdes channels to illustrate the advantages of developing ML based techniques for packaging related to Signal, Power and Thermal Integrity. Fundamentals associated with surrogate modeling, Gaussian process, Bayesian methods, neural networks, sensitivity analysis, etc will be discussed during the course of this tutorial

Madhavan Swaminathan Madhavan Swaminathan is the John Pippin Chair in Microsystems Packaging & Electromagnetics in the School of Electrical and Computer Engineering (ECE) and Director of the 3D Systems Packaging Research Center (PRC), GT. He also serves as the Site Director for CAEML, an NSF Industry University Cooperative Research Center. He formerly held the position of Founding Director, Center for Co-Design of Chip, Package, System (C3PS), Joseph M. Pettit Professor in Electronics in ECE and Deputy Director of the Packaging Research Center (NSF ERC), GT. Prior to joining GT, he was with IBM working on packaging for supercomputers. He is the author of 500+ refereed technical publications, holds 30 patents, primary author and co-editor of 3 books, founder and co-founder of two start-up companies, and founder of the IEEE Conference Electrical Design of Advanced Packaging and Systems (EDAPS), a premier conference sponsored by the EPS society. He is an IEEE Fellow and has served as the Distinguished Lecturer for the IEEE EMC society. He received his MS/PhD degrees in Electrical Engineering from Syracuse University in 1989 and 1991, respectively.