EPEPS 2018: San Jose, California
IEEE
Tutorial V
Advances in Package Technologies and Impact to Electrical Performance

Kemal Aygun, Principal Engineer and Manager, Intel

Fueled by the developments in technologies from artificial intelligence to internet of things and from next generation 5G communication to autonomous driving, the electronics industry is going through some rapid changes. As the new electronics systems need to provide increasingly higher performance in these emerging segments, the capability of the components that constitute these systems also needs to scale accordingly. One area where pace of innovation has greatly increased recently is packaging. In addition to maintaining and scaling the historical functions, such as providing mechanical stability, thermal dissipation, power delivery, and input/output (IO) data transfer to a silicon die, the new era of packaging also needs to pave the way to ultimate system-in-packages (SiPs) via heterogeneous integration. These new SiPs have to integrate multiple logic, memory, and other specialized silicon dies, potentially using different silicon process technologies, and have to provide unprecedented levels of performance in metrics such as IO bandwidth, bandwidth density, and power efficiency. This tutorial will review some of the recent advances in packaging from scaling of traditional technologies to new emerging technologies such as fan-out level and 2.xD packaging. It will also summarize some of the key impacts of these new technologies on electrical performance both in terms of improvements and new challenges.