EPEPS 2018: San Jose, California
Tutorial V
High Speed Bus Channel Signal Integrity Analysis from Concept to Hardware

Jose Hejase, IBM

Signal integrity (SI) simulations of high speed link channels are an integral part of the design process of high speed communication buses in computer server systems. At early concept design, the simulations predict channel signal integrity performance at the desired bit-rate, and the results are utilized for a multitude of reasons including the determination of wiring guidelines and design practices that need to be followed by physical layout designers. Sensitivity analysis is done to evaluate the impact of deviations from wiring guidelines and whether they are acceptable from an overall channel performance point of view. In addition, predicting the channel performance impact of package and PCB manufacturing tolerances and preparing for correlation studies with hardware measured results will prepare the designer to produce a product for efficient, one-pass design. Channel simulations increase in importance as bus data rates increase as key channel SI properties such as reflections, crosstalk and loss become more significant as the unit interval becomes smaller.

In this presentation, 25Gb/s high-speed link channel pre-route analysis and post-route verification simulations performed on IBM POWER9 high-performance computing (HPC) systems are presented. The channel 2D and 3D electromagnetic models representing the high-speed link channel are described along with the methodology and assumptions used to derive the models. The pre-route design models include worst case PCB manufacturing tolerances and represent the different sections of the channel with a worst-case reflection, length (loss), and crosstalk assumption, but without exactly representing an individual channel wiring detail. The post-route channel models extract the wiring as it exists in the board design without worst-case manufacturing tolerances.

The channels’ frequency-domain properties generated using the two sets of models are analyzed and compared. The transmitter and receiver circuits using the time-domain simulator are simulated with the S-Parameters of the channel segments to create eye diagrams. The channel simulation results from both pre-route and post-route extraction of representative channels are compared to measured eye opening results from laboratory hardware. Observations on how modeling and simulations enable the SI engineer and the physical designer to successfully implement high-speed channels conclude the presentation.