Tutorial 1
Advanced Packaging for High-Speed Chiplet Interconnects: Technologies, Methodologies, and Standards

Kemal Aygün, Intel

With the rapid growth of artificial intelligence, high-performance computing, and data-centric applications, future electronic systems must deliver significantly higher levels of bandwidth and performance. A key enabler of this scaling is advanced system-in-package integration, where multiple dies and chiplets are interconnected through increasingly dense and high-speed interconnect architectures.

This tutorial reviews recent developments in advanced electronic packaging technologies for high-speed electrical and optical interconnects. Topics include 2D, 2.5D, and 3D integration architectures, signal integrity challenges, and modeling and characterization methodologies. The tutorial will also summarize current die-to-die and chiplet interface standardization efforts and discuss future scaling trends and challenges for heterogeneous integration.

The tutorial is intended for engineers, researchers, and students seeking an overview of the technologies, methodologies, and standards shaping the next generation of chiplet-based systems.

Kemal Aygün is an Intel Fellow in the Intel Foundry Technology Development organization, where he leads the development of high-bandwidth package and socket technologies, as well as modeling and characterization methodologies for on- and off-package I/O interfaces. He served as General Chair of the 2020 IEEE Electrical Performance of Electronic Packaging and Systems (EPEPS) Conference and is an IEEE Fellow and Distinguished Lecturer of the IEEE Electronics Packaging Society (EPS). Dr. Aygün received his Ph.D. in Electrical and Computer Engineering from the University of Illinois at Urbana-Champaign.