Tutorial 1
Vertical Power Delivery for High-Density Computing: Challenges and Opportunities

Inna Partin‑Vaisband, McGill University

The design of modern power delivery systems is at a turning point to enable future high performance computing systems and AI applications. Traditional high-voltage power converters, typically implemented on printed circuit boards (PCBs), have matured to efficiently deliver bulk power at the system level. In parallel, integrated voltage regulators (IVRs) have become essential for delivering fine-grain, low-noise power on-chip. Vertical power delivery (VPD) combines these two previously disjointed domains, creating a fundamentally new design paradigm that tightly integrates off-chip conversion efficiency with on-chip regulation fidelity. VPD collapses the hierarchical stack, bringing voltage regulation into the vertical die-stack proximity of high-performance ICs, and therefore demands innovation in circuits, devices, and co-design methodologies. As a result, the challenges traditionally addressed in separate communities—such as high-voltage device modeling, circuit-level noise resilience, in-situ control, and floorplan-aware delivery—must now be understood in a unified context. This convergence offers transformative opportunities, but also exposes gaps in existing design infrastructure, modeling, and abstraction.

This tutorial will provide a system-to-device perspective on VPD and highlight open research challenges in achieving high-efficiency, high-density, and scalable power delivery. Topics will include distributed and stackable VPD architectures for ultra-high current (up to 50 kA) and high current density (2-4 A/mm2 on average and up to 10 A/mm² peak) targets, efficient conversion from high-voltage rails (e.g., 48V/12V-to-1V), and integrated power management across densely stacked heterogeneous systems. We will discuss hybrid voltage regulator design and opportunities for co-design across the vertical hierarchy. Emphasis will be placed on identifying methodological and modeling gaps and outlining promising directions toward systematic VPD implementation for next-generation heterogeneous platforms.

Inna Partin‑Vaisband is an Associate Professor of Electrical and Computer Engineering at the University of Illinois Chicago. She earned her B.Sc. in Computer Science and M.Sc. in Electrical Engineering from the Technion–Israel Institute of Technology, and her Ph.D. in Electrical and Computer Engineering from the University of Rochester. Between 2004 and 2009, she was with R&D IBM Haifa.

Her research focuses on power delivery and management, analog and mixed‑signal circuit design, AI‑guided design automation, and hardware security with applications in edge‑learning and chiplet‑based systems. She is the author of On‑Chip Power Delivery and Management (4th Ed.), and her distributed on‑chip power‑supply architectures have been deployed in commercial mobile SoCs as part of the Qualcomm Snapdragon product line. Her work on chiplet‑based systems was featured in Communications of the ACM (2024). She serves as an Associate Editor for Microelectronics Journal and IEEE Transactions on CPMT and is a recipient of the 2022 Google Research Scholar Award and the 2023 NSF CAREER Award.