Tutorial 4
High-speed Interconnect Design for next-gen AI Hardware

Rohit Sharma, IIT Ropar

Advancements in computing and high-speed wireless communications have led to the need for heterogeneously integrated packages and systems capable of higher throughput with lower energy consumption. This approach differs from previous methods that advanced each component individually and then integrated all necessary components onto system boards. Electronic package design is a significant aspect of the electronics industry. The current design paradigm emphasizes integrated chip-package co-design.

This tutorial examines the crucial role of high-speed interconnect design in next-generation AI hardware, which facilitates efficient data transfer among processing units. As the computational demands of AI workloads continue to grow, it is imperative that interconnects deliver ultra-low latency, high bandwidth, and optimal energy efficiency. Emerging technologies—such as photonic interconnects, chiplet-based architectures, and high-speed SerDes—are integral to overcoming these challenges. The abstract discusses innovative design strategies, including coherent interconnect protocols and 3D integration, aimed at optimizing data movement within AI systems. By alleviating bottlenecks and improving scalability, these approaches support robust performance for large-scale AI models and contribute to significant advancements in machine learning and data processing.

This tutorial reviews advanced electrical design for packages and systems, focusing on signal and power integrity, codesign for improved reliability, and an overview of machine learning through system-level integration. Key topics include electronic packaging, heterogeneous integration, chip-to-chip signaling, and high-speed interconnect design. It addresses transmission line analysis and related challenges like delay, crosstalk, noise, and eye diagrams, concluding with the importance of chip-package co-design for system performance.

Rohit Sharma joined the Electrical Engineering department at IIT Ropar in 2012, where he is currently a professor. In the past, he has been a Visiting Professor at the Small-Scale Systems Integration and Packaging Center, Binghamton University (May - Jul 2022), and the Packaging Research Center, Georgia Institute of Technology (Sep 2022 - Feb 2023). He was a Research Professor in the Department of Electrical Engineering at Pennsylvania State University, USA (Mar 2023 - Apr 2024).

He is a Distinguished Lecturer of the IEEE Electronics Packaging Society, an Associate Editor for the IEEE Transactions on Components, Packaging and Manufacturing Technology, and a referee for several leading IEEE journals. He is a Program Committee member for major IEEE EPS conferences including ECTC, EDAPS, EPEPS, and SPI. He has chaired the IEEE CPMT Technical Committee on Electrical Design, Modeling and Simulation. He is a Fellow of the Institution of Engineering and Technology (IET), UK, and the Institution of Electronics and Telecommunication Engineers (IETE), India, as well as a Senior Member of the IEEE.

His research interests include the design of high-speed chip-chip and on-chip interconnects, graphene-based nanoelectronic devices and interconnects, signal and thermal integrity in high-speed interconnects, and the application of machine learning in advanced packaging and systems.