Tutorial 6
Signal integrity Engineering With Superconductors: An Introduction

Soumitra Joy , University of North Carolina at Charlotte

Exascale computing for next generation AI data centers demands massive parallelism of integrated chips on package, with data-exchange among chips at terabyte-per-second (TB/s) bandwidth. This vision is severely constrained by two intertwined bottlenecks: i) limited bandwidth of the interconnect owing to their RC delay, and ii) thermal management challenges resulting from dense devices operating at high-speed. Ironically, approaches that reduce electrical losses often degrade thermal performance. For instance, porous, non-crystalline low-k substrates minimize parasitic capacitance, but their disordered structures and air pockets drastically reduce thermal conductivity. To navigate this complex scenario, it's essential for today's and future engineers to have a strong command of both electrical and thermal performance analysis techniques in electronic packaging.

In the first half of this tutorial, we will discuss how key signal integrity metrics—such as propagation loss, crosstalk, and delay—relate directly to geometric features and material choices of interconnects. Concurrently, we will examine how thermal performance, including temperature profiles and hotspot generation, is also tied to interconnect design. This session will present how temperature, in turn, impacts interconnect performance through thermal noise, compromised conductivity, and long-term reliability, and how an equivalent electrical circuit model can be used for electrical and thermal co-design of interconnects.

The second half of the tutorial will introduce an emerging alternative interconnect technology: electromagnetic surface-wave interconnects at a deep subwavelength scale. This technology employs engineered waveguides whose electrical transmission is optimized solely through metal interface engineering, allowing for independent selection and design of the bulk substrate for enhanced thermal performance. This decoupling of electrical and thermal optimization is a critical step toward ultra-high-speed computing. We will discuss techniques of designing and analyzing surface-wave interconnects, highlight the current status of this nascent technology and the key challenges that lie ahead for its integration into advanced packaging.